EE 7530
VLSI Design Synthesis and Optimization
Wright State University-Main Campus · UGRD · Fall 2026
1 section
Catalog description
VLSI Synthesis and optimization including data path synthesis, glue logic synthesis control-unit synthesis, and resource sharing. Covers behavioral level to layout level synthesis and corresponding algorithms. Department Managed Prerequisite(s): (Undergraduate level EE 4620 Minimum Grade of D and Undergraduate level EE 4620L Minimum Grade of D) or (Graduate level EE 6620 Minimum Grade of C and Graduate level EE 6620L Minimum Grade of C)
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Availability not recently verifiedClass #wright_main_campus-EE7530Fall 2026UGRD3 credits
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