EE 2000

Digital Design with HDL

Wright State University-Main Campus · UGRD · Fall 2026

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Introduction to combinational and synchronous sequential digital system design and optimization. Use of structural hardware description language (HDL) with CAD tools for design and simulation in a field programmable gate array (FPGA) based laboratory environment. Design and testing of simple combinational and synchronous sequential circuits. Corequisite(s): EE2000L Course Level: Undergraduate Schedule Type(s): Lecture Grade Mode: Standard An additional fee is associated with this course.

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Class #wright_main_campus-EE2000Fall 2026UGRD3 credits
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