BEE 427
Introduction to Digital System Design Using Hardware Description Languages
University of Washington-Bothell Campus · UGRD · Fall 2026
1 section
Catalog description
Modeling techniques with the Verilog hardware description language; methodologies for finite-state machine (FSM) design, register-transfer level (RTL) design, and datapath and control unit design; computer arithmetic algorithms; and fast arithmetic hardware architectures. Prerequisite: a minimum grade of 1.7 in B EE 271.
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Availability not recently verifiedClass #washington_bothell_campus-1082Fall 2026UGRD5 credits
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