ECE 351

CMOS VLIS Laboratory

Trine University · UGRD · Fall 2026

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The lab provides an extensive opportunity to implement complementary metal oxide semiconductor (CMOS) very large-scale integration (VLSI) design concepts. Students will: Use CMOS techniques to design and predict the performance of NOT/NAND/AND/NOR/OR logic gates; design area and delay-constrained 8-bit equality comparator, adder, and multiplexer circuits; design transistors to drive large loads; design an 8-bit low power ALU circuit with PAD frames. Corequisite: ECE 353

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Class #trine_regional_non_traditional_c-0497Fall 2026UGRD1 credits
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