GEN 5631

Silicon Bring-Up: Post-Silicon Validation and Characterization

Stanford University · UGRD · Fall 2026

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This hands-on course guides students through the complete workflow of bringing up and validating a fabricated integrated circuit in a modern CMOS process. The course uses chips designed and fabricated in a preceding tapeout course, in which students design and fabricate analog low-dropout (LDO) regulators; however, prior participation in the design course is not required. Students will learn to interface with packaged devices, develop measurement setups, and use industry-standard lab equipment to characterize performance. Topics include PCB and test fixture design, automated data collection, post-silicon characterization across process, voltage, and temperature, and systemic debug of discrepancies between simulation and measurement. Working in small teams, students will bring up fabricated designs, diagnose silicon-level issues, and complete a full validation and debug cycle, culminating in a final report and demonstration.

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Class #stanford-5631Fall 2026UGRD3 credits
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