Hardware Description Language

Catalog description

This course is a more in depth coverage of current logic design and verification methodologies using a modern hardware description language (HDL). Topics include coding for different levels of abstraction; implementation of arithmetic circuits and finite state machines, hierarchical designs, reusable component design, data and control path, best coding practices, design constraints and verification. The laboratories are designed to illustrate concepts, reinforce analysis and design skills, and develop instrumentation techniques associated with the lecture topics.