Hardware Description Language

Catalog description

This course is a more in depth coverage of current logic design and verification methodologies using a modern hardware description language (HDL). Topics include coding for different levels of abstraction, implementation of arithmetic circuits and finite state machines, hierarchical designs, reusable component design, data and control path, best coding practices, design constraints and verification. Students, upon completion of this course, will have the necessary skills to analyze and design advanced hardware descriptions of combinational and sequential logic circuits using design and verification best practices and methodologies.