Design and Test of Multi-Core Chips

Catalog description

Massive levels of integration following Moore’s Law is making modern multi-core chips all-pervasive in several domains ranging from scientific applications like weather forecasting, astronomical data analysis, bioinformatics applications to even consumer electronics. This course introduces students to current and future trends in IC Design. Students learn to identify bottlenecks in designing state-of-the-art multicore System-on-Chips (SoCs) and propose solutions to such design challenges from a cross-layer perspective spanning multiple levels of abstraction in the design process. Low-power and high-speed testing of multicore chips is an important design issue in Design for Testability (DFT) of such massive multicore systems. In this course students learn various issues and solutions to ongoing challenges in SoC testing. The instruction will rely on lectures, textbooks, seminal and cutting edge publication articles and term projects. Students will be evaluated based on homework assignments, class presentations, examinations and projects.