Computer Architecture

Catalog description

The course covers various aspects of advanced uniprocessor computer architecture design. Instruction set architecture design alternatives are discussed with emphasis on the Reduced Instruction Set Computer (RISC) architecture. Techniques to enhance CPU performance such as pipelined execution optimizations, conditional branch handling techniques, exploitation of instruction-level parallelism, multiple-instruction issue, and dynamic scheduling are studied. Cache, and memory hierarchy design and performance issues are also presented. The design aspects of efficient and reliable input/output systems are also covered. The course concludes with an introduction to concepts of multiprocessor systems design.