High Speed Interface Circuits and Systems Design

Catalog description

Analysis and design of link architectures and circuits for wireline communication systems. Emphasis on design intuition, link budgeting and power/performance trade-offs in implementation of data links in advanced CMOS process. Topics include channel characterization, noise analysis, equalization, transmitter and receiver circuits, signaling schemes, clocking, synchronization and timing recovery. Prereq or concur: 5020 and 5021, or permission of instructor.