Digital Integrated Circuits Laboratory

Catalog description

Laboratory work and a design project are intended verification of CMOS logic circuits. Laboratory exercises to cover CMOS propagation Delay and Layout Parasitics, Gate Styles, CMOS Arithmetic Blocks, Bipolar Devices, Bipolar Devices Propagation Delay, Very High Speed Combinational Logic, Sequential Circuits, Sequential Circuits and Timing Issues, Memory and Array Structures are also done.