Low Power and Robust CMOS Design

Catalog description

the increased power consumption in portable devices has been one of the most important challenges in VLSI design which occurs due to the high performance of chips. The aim of this course is to create reliable low power designs that are also tolerant to soft errors. the course starts with a discussion on increasing leakage power consumption and identifies various mechanisms responsible for the increase such as sub-threshold leakage and gate and junction leakage. It then covers circuit-level leakage control techniques used by industry such as transistor stacking and multi VTH and body-biasing. The second part of the course addresses soft error issues in commercial VLSI. The impact of lower power designs on radiation tolerance is studies and results are shown using the industry grade HSpice simulation tool involving advanced benchmark circuits.