Complex Digital ASIC Design

Catalog description

Principles and practices involved in the design, implementation, testing, and evaluation of complex standard-cell ASIC chips using automated state-of-the-art CAD tools. Topics include hardware description languages; CMOS logic, state, and interconnect fundamentals; chip design methodologies; automated cell-based design; CAD algorithms; details of accurately modeling ASIC delay, energy, and area; robustness issues; testing, verification, and debugging; power distribution and clocking; packaging and I/O. Includes a six-week open ended project where small groups of students design, implement, test, and evaluate an interesting technique in computer architecture using functional-, microarchitectural-, registertransfer-, and layout-level modeling.