Digital ASIC Design

Catalog description

This course aims to provide a strong foundation for students to understand the principle and practice of designing, implementing, testing, and evaluating standard-cell ASIC chips using automated state-of-the-art electronic design automation (EDA) tools. Topic include both basic and advanced CMOS devices, standard cells, memories, front-end flows, and back-end flows. The course includes three design projects completed in small groups. In the first design project, students build their own simple EDA toolflow including a small standard cell library, synthesis algorithm, and place-and-route algorithm to enable mapping a combinational hardware design to layout. In the second design project, students transition to using a commercial standard-cell library and commercial EDA tools for simulation, synthesis, place-and-route, static-timing analysis, power analysis, design rule checking, and layout-vs-schematic checking of a hardware accelerator of their choosing. In the third open-ended design project, students will design, implement, test, and evaluate an interesting technique in computer architecture in the context of a more complex system-on-chip.