Digital System Testing and Testable Design

Catalog description

For this course, time- and topic-indexed videos of lecture, homework, projects, etc. will be available from the online learning portal/website. In addition to these resources, two 1-hour live sessions are scheduled per week for recitation. Each student is strongly urged to attend one of these two sessions each week, either remotely or in the classroom on the Carnegie-Mellon Pittsburgh campus. This course examines in depth the theory and practice of fault analysis, test generation, and design for testability for digital ICs and systems. The topics to be covered include circuit and system modeling; fault sources and types; the single stuck-line (SSL), delay, and functional fault models; fault simulation methods; automatic test pattern generation (ATPG) algorithms for combinational and sequential circuits, including the D-algorithm, PODEM, FAN, and the genetic algorithm; testability measures; design-for-testability; scan design; test compression methods; logic-level diagnosis; built-in self-testing (BIST); VLSI testing issues; and processor and memory testing. Advance research issues, including topics on MEMS and mixed-signal testing are also discussed. 4 hours of lecture per week Prerequisites: 18-240 and 15-211 and ( 18-340 or 18-341 ) Senior or graduate standing required. Prerequisites: 15-210 Min. grade C and 18-240 Min. grade C and ( 18-341 Min. grade C or 18-340 Min. grade C) Course Website: http://www.ece.cmu.edu/~ee765/