Advanced Topics in Logic Design.

Catalog description

Synchronous and asynchronous state machines. Timing issues in high-speed digital design. Design of a complex system using VHDL and Verilog Hardware Description Languages in a CAD environment. Automation toolsets to synthesize projects containing a hierarchy of modules into Field Programmable Gate Arrays (FPGAs). Simulations using CAD tools to verify the design before implementation on rapid prototyping boards in the lab. Lecture 3 hours; laboratory 3 hours.