Computer-Aided Systems Design and Verification.

Catalog description

Design and verification methodology using hardware description and verification languages (HDVLs). Advances in IC chip design; introduction to HDVLs such as System Verilog; HDVL language basics including data types, arrays, structures, unions, procedural blocks, tasks, functions, and interface concepts; design hierarchy; verification planning and productivity; verification infrastructure; guidelines for efficient verification of large designs; assertion-based verification; comprehensive computer-related design projects.