CPE 166

Advanced Logic Design.

California State University, Sacramento · UGRD · Fall 2026

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VHDL and Verilog Hardware Description Languages are studied and used on the following advanced level logic design topics: synchronous state machines, asynchronous state machines, metastability, hazards, races, testability, boundary scan, scan chains, and built-in self-tests. Commercial Electronic Design Automation (EDA) toolsets are used to synthesize lab projects containing a hierarchy of modules into Field Programmable Gate Arrays (FPGAs). Post synthesis simulations by these same tools verify the design before implementation on rapid prototyping boards in the lab.

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Class #california_state_sacramento-1298Fall 2026UGRD4 credits
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