ECE 3300L
Digital Circuit Design Using Verilog Laboratory
California State Polytechnic University-Pomona · UGRD · Fall 2026
4 sections
Sections
Current meeting, instructor, credit, and enrollment details
01
Availability not recently verifiedClass #74142Fall 2026UGRD1 credits
- Days & times
- Mo We · 1:00 – 2:15 PM
- Meeting dates
- 2026-08-20 to 2026-12-13
- Location
- 9 503
- Instructor
- Aly, Mohamed
02
Availability not recently verifiedClass #74143Fall 2026UGRD1 credits
- Days & times
- Tu · 4:00 – 6:50 PM
- Meeting dates
- 2026-08-20 to 2026-12-13
- Location
- 9 435
- Instructor
- Ramos-Giron, Gerson
03
Availability not recently verifiedClass #74144Fall 2026UGRD1 credits
- Days & times
- Mo · 7:00 – 9:50 PM
- Meeting dates
- 2026-08-20 to 2026-12-13
- Location
- 9 435
- Instructor
- Van Blerkom, Daniel
04
Availability not recently verifiedClass #76119Fall 2026UGRD1 credits
- Days & times
- Th · 1:00 – 3:50 PM
- Meeting dates
- 2026-08-20 to 2026-12-06
- Location
- 9 503
- Instructor
- Gaon, Jack
Class numbers and section codes come from the registrar.
Spot missing or incorrect course data?