ECE 3300
Digital Circuit Design Using Verilog
California State Polytechnic University-Pomona · UGRD · Fall 2026
3 sections
Sections
Current meeting, instructor, credit, and enrollment details
01
Availability not recently verifiedClass #74139Fall 2026UGRD3 credits
- Days & times
- Mo We · 11:30 AM – 12:45 PM
- Meeting dates
- 2026-08-20 to 2026-12-13
- Location
- 9 307
- Instructor
- Aly, Mohamed
02
Availability not recently verifiedClass #74140Fall 2026UGRD3 credits
- Days & times
- Mo We · 1:00 – 2:15 PM
- Meeting dates
- 2026-08-20 to 2026-12-13
- Location
- 9 409
- Instructor
- Yin, Meng-Lai
03
Availability not recently verifiedClass #74141Fall 2026UGRD3 credits
- Days & times
- No scheduled meeting time
- Meeting dates
- 2026-08-20 to 2026-12-13
- Location
- —
- Instructor
- Van Blerkom, Daniel
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