Digital ASIC Design

Catalog description

The design of complex digital Application Specific Integrated Circuits (ASICs). Standard cell libraries and the Verilog language are used to build complex digital synchronous circuits using Cadence layout synthesis tools. Interconnect delay estimation, clock tree synthesis, repeater and pipeline stage design are introduced. A synchronous digital circuit utilizing 100s of flip flops and digital gates is designed as a final project and sent to MOSIS for fabrication. Prerequisite(s): I ECE 420.